Oversampling circuit digital/analog converter

ABSTRACT

It is object to provide an oversampling circuit and a digital to analog converter capable of realizing a smaller circuit and reducing a cost of parts. The oversampling circuit comprises four D flip-flops  10 - 1  through  10 - 4 , four multipliers  12 - 1  through  12 - 4 , three adders  14 - 1  through  14 - 3 , and two integrating circuits  16 - 1  and  16 - 2 . Input data is sequentially input into the four D flip-flops, and held therein. Each multiplier performs a multiplying process on the data held in the D flip-flops respectively corresponding one to one to the multipliers by different multiplicators in the first half and second half of one clock period. The multiplication results are added up by the three adders. Furthermore, two digital integrating operations corresponding to the sum are carries out by means of the two-integrating circuits.

TECHNICAL FIELD

The present invention relates to an over sampling circuit forinterpolating input data discretely and a digital-to-analog converter towhich the oversampling circuit is applied. In this specification, it isassumed that a case where function values have finite values except zeroin a local region and become zero in regions different from the regionis called a “local support.”

BACKGROUND ART

A recent digital audio apparatus, for example, a CD (Compact Disk)player, uses a D/A (digital-to-analog) converter to which anover-sampling technique is applied to obtain a continuous analog audiosignal from discrete music data (digital data). Such a D/A convertergenerally uses a digital filter to raise a pseudo sampling frequency byinterpolating input digital data, and outputs smooth analog audiosignals by passing each interpolation value through a low-pass filterafter generating a staircase signal waveform with each interpolationvalue held by the sample holding circuit.

A data interpolation system disclosed in WO99/38090 is well known as amethod of interpolating data into discrete digital data. In this datainterpolation system, differentiation can be performed only once in thewhole range, and a sampling function is used such that two samplingpoints each before and after an interpolation position, that is, a totalof four sampling points, can be considered. Since the sampling functionhas values of a local support unlike the sinc function defined by sin(πft)/(πft) where f indicates a sampling frequency, there is a meritthat no truncation errors occur although only four pieces of digitaldata are used in the interpolating operation.

Generally, oversampling is performed by using a digital filter in whichthe waveform data of the above mentioned sampling function is set to atap coefficient of an FIR (finite impulse response) filter.

If the oversampling technology of performing an interpolating operationfor discrete digital data using the above mentioned digital filter, alow pass filter having a moderate attenuation characteristic can beused. Therefore, the phase characteristic with a low pass filter canapproach a linear phase characteristic, and the sampling aliasing noisecan be reduced. These effects are more outstanding with a higheroversampling frequency. However, if the sampling frequency becomeshigher, the number of taps of the digital filter is also increased. As aresult, there arises the problem of a larger circuit. In addition, theperformance of the delay circuit or multiplier comprises the digitalfilter is also sped up. Therefore, it is necessary to use expensiveparts appropriate for the quick performance, thereby increasing the costof the required parts. Especially, when the oversampling process isperformed using a digital filter, an actual value of a sampling functionis used as a tap coefficient. Therefore, the configuration of amultiplier is complicated, and the cost of the parts furthermoreincreases.

Moreover, although a digital-to-analog converter can be configured byconnecting a low pass filter after the oversampling circuit, the abovementioned various problems with the conventional oversampling circuithave also occurred with the digital-to-analog converter configured usingthe circuit.

BRIEF SUMMARY OF THE INVENTION

The present invention has been achieved to solve the above mentionedproblems, and aims at providing an oversampling circuit and adigital-to-analog converter having a smaller circuit at a lower cost ofparts.

In the oversampling circuit according to the present invention, aplurality of data holding unit hold plural pieces of digital data inputat predetermined intervals, and a plurality of multiplying unit performmultiplying processes using respective multiplicators for the first andthe second of the data holding periods on the digital data held in therespective data holding unit. By performing digital integration pluraltimes on the digital data obtained by adding unit adding upmultiplication results, digital data whose values change stepwise isoutput along a smooth curve. Thus, the multiplication resultscorresponding to sequentially input plural pieces of digital data areadded up, and then the digital integration is performed on the additionresult. As a result, output data whose values smoothly change can beobtained. Therefore, when an oversampling frequency is high, it isnecessary only to speed up the digital integration, thereby avoiding theconventional complicated configuration, that is, simplifying theconfiguration, and reducing the cost of parts.

Each of the multiplicators used in the multiplying processes by theplurality of multiplying unit is desired to correspond to each of thevalues of step functions obtained by differentiating plural timespiecewise polynomials for a predetermined sampling function configuredby the piecewise polynomials. That is, by integrating plural times theabove mentioned step function, a waveform corresponding to thepredetermined sampling function can be obtained. Therefore, aconvolution operation using a sampling function can be equivalentlyrealized by generating a step function. As a result, the contents of theentire process can be simplified, and the number of processes requiredoversampling can be successfully reduced.

In addition, the above mentioned step function is desired to equally setthe positive and negative areas. Thus, the divergence of integrationresults of the integrating unit can be prevented.

Furthermore, it is desirable that the above mentioned sampling functionhas a value of local support with the whole range differentiable onlyonce. It is assumed that a natural phenomenon can be approximated if thewhole range is differentiable only once. By setting a smaller number oftimes of differentiation, the times of the digital integration performedby the integrating unit can be reduced, thereby successfully simplifyingthe configuration.

It is further desirable that the above mentioned step function containsan area of eight piecewise sections in equal width weighted by −1, +3,+5, −7, −7, +5, +3, and −1 in a predetermined range corresponding tofive pieces of digital data arranged at equal intervals, and that everytwo of the eight weight coefficients are set as the multiplicators inthe respective multiplying unit. Since simple weight coefficientsrepresented by integers can be used as the multiplicators in each of therespective multiplying unit, the multiplying process can be simplified.

Especially, it is desirable that a multiplying process performed in eachof the plurality of multiplying unit is represented by adding digitaldata to an operation result of the exponentiation of 2 by a bit shift.Since the multiplying process can be replaced with a bit shift processand an adding operation, the configuration can be simplified and theprocess can be sped up by simplifying the contents of the processes.

It is also desirable that the times of the digital integration is two,and an data whose value changes like a quadric function is output fromthe integrating unit. For smooth interpolating plural pieces of discretedata, it is necessary at least to change a value like a quadricfunction. Since it can be realized only by setting the number of timesof the digital integration to 2, the configuration of the integratingunit can be simplified.

Furthermore, the digital integration performed by the integrating unitis a process of accumulating input data, and it is desirable that theprocess is repeated n times in a period of inputting digital data intothe data holding unit. Thus, the operation of accumulating data can berealized only by adding input data to held data. Therefore, theconfiguration of the integrating unit can be simplified, and the processcan be easily and more quickly repeated. As a result, the value of themultiple n of the oversampling can be set to a large value withoutcomplicating the configuration and largely increasing the cost of parts.

In addition, the digital-to-analog converter can be configured only byproviding voltage generation unit and smoothing unit at the stage afterthe above mentioned oversampling circuit. Accordingly, thedigital-to-analog converter according to the present invention can berealized with a simplified configuration and reduced cost of parts.Furthermore, the above mentioned oversampling circuit can easily set ahigh oversampling frequency without complicating the configuration orlargely increasing the cost of parts. As a result, the distortion of theoutput waveform of the digital-to-analog converter to which theoversampling circuit is applied can be minimized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a sampling function used in an interpolatingoperation in the oversampling circuit according to an embodiment;

FIG. 2 is a diagram showing a relationship between the sampling valueswith an interpolation values;

FIG. 3 is a diagram showing a waveform obtained by differentiating oncethe sampling function shown in FIG. 1;

FIG. 4 is a diagram showing a the waveform obtained by furtherdifferentiating the polygonal line function shown in FIG. 3;

FIG. 5 is a diagram showing a the configuration of an oversamplingcircuit of an embodiment;

FIG. 6 is a block diagram showing a detailed configuration of anintegrating circuit included in the oversampling circuit shown in FIG.5;

FIGS. 7A through 7L are charts showing the operation timings of theoversampling circuit of an embodiment;

FIGS. 8A and 8B are diagrams showing detailed data output from theintegrating circuits;

FIG. 9 is a diagram showing a detailed configuration of the multiplier;

FIG. 10 is a diagram showing a detailed configuration of the multiplier;

FIG. 11 is a diagram showing a detailed configuration of the multiplier;

FIG. 12 is a diagram showing a detailed configuration of the multiplier;

FIG. 13 is a diagram showing a detailed configuration of the multiplier;

FIG. 14 is a diagram showing a detailed configuration of the multiplier;

FIG. 15 is a diagram showing a detailed configuration of the multiplier;

FIG. 16 is a diagram showing a detailed configuration of the multiplier;and

FIG. 17 is a diagram showing a configuration of the D/A converter towhich the oversampling circuit shown in FIG. 5 is applied.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the oversampling circuit according to the presentinvention is described below in detail by referring to the attacheddrawings. FIG. 1 shows a sampling function used in an interpolatingoperation in the oversampling circuit according to the presentembodiment. The sampling function H(t) is disclosed by WO99/38090, andrepresented by the following expressions.

(−t ²−4t−4)/4;−2≦t<−3/2

(3t ²+8t+5)/4;−3/2≦t<−1

(5t ²+12t+7)/4;−1≦t<−1/2

(−7t ²+4)/4;−1/2≦t<0

(−7t ²+4)/4;0≦t<1/2

(5t ²−12t+7)/4;1/2≦t<1

(3t ²−8t+5)/4;1≦t<3/2

(−t ²+4t−4)/4;3/2≦t≦2  (1)

where t=0, ±1, ±2 indicates the sampling position. The sampling functionH(t) shown in FIG. 1 can be differentiated only once in the whole range,and is a function of local support converging into 0 with the samplingposition t=±2. By performing an overlapping process using the samplingfunction H(t) based on each sampling value, the interpolating processcan be performed using a function differentiable only once in thesampling values.

FIG. 2 shows the relationship between the sampling values and theinterpolation values. As shown in FIG. 2, assume that four samplingpositions are t1, t2, t3, and t4, and the distance between two adjacentsampling positions is 1. The interpolation value y corresponding to theinterpolation position t0 between the sampling positions t2 and t3 isobtained by the following equation.

y=Y(t1)·H(1+a)+Y(t2)·H(a)+Y(b 3)·H(1−a)+Y(t4)·H(2−a)  (2)

where Y (t) indicates each sampling value at the sampling position t.Each of 1+a, a, 1−a, and 2−a indicates the distance between theinterpolation position t0 and each of the sampling positions t1 throught4.

As described above, by performing a convolution operation by computingthe value of the sampling function H(t) corresponding to each samplingvalue, an interpolation value of sampling values can be obtainedtheoretically. However, the sampling function shown in FIG. 1 is aquadric piecewise polynomial differentiable only once in the wholerange. Using this feature, the interpolation value can be obtained inanother equivalent process procedure.

FIG. 3 shows a waveform obtained by differentiating once the samplingfunction shown in FIG. 1. The sampling function H(t) shown in FIG. 1 isa quadric piecewise polynomial differentiable once in the entire range.Therefore, by performing the differentiation once, a polygonal linefunction formed by the waveform of a continuous polygonal line as shownin FIG. 3 can be obtained.

FIG. 4 shows the waveform obtained by further differentiating thepolygonal line function shown in FIG. 3. However, the polygonal linewaveform contains a plurality of corner points, and the differentiationcannot be performed in the whole range. Therefore, the differentiationis performed on the linear portion between two adjacent corner points.By differentiating the polygonal line waveform shown in FIG. 3, the stepfunction formed by the stepwise waveform as shown in FIG. 4 can beobtained.

Thus, the above mentioned sampling function H(t) is once differentiatedin the entire range to obtain a polygonal line function. By furtherdifferentiating each of the linear portions of the polygonal linefunction, a step function can be obtained. Therefore, in the reverseorder, by generating the step function shown in FIG. 4, and integratingit twice, the sampling function H(t) shown in FIG. 1 can be obtained.

In the step function shown in FIG. 4, the positive and negative areasare set equal to each other, and the sum of the areas equals 0. That is,by integrating such a step function plural times, a sampling function oflocal support, as shown in FIG. 1, whose differentiability in the wholerange is guaranteed can be obtained.

In computing the interpolation value in the convolution operation shownby the equation (2), the value of the sampling function H(t) ismultiplied by each sampling value. If the sampling function H(t) isobtained by integrating twice the step function shown in FIG. 4, thevalue of the sampling function obtained in the integrating process ismultiplied by each sampling value, or equivalently, when a step functionbefore the integration processing is generated, an interpolation valuecan be obtained by generating a step function by multiplication by eachsampling value, and performing twice the integrating process on theresult obtained in the convolution operation using the step function.The oversampling circuit according to the present embodiment obtains aninterpolation value as described above. This process is described belowin detail.

FIG. 5 shows the configuration of the oversampling circuit according tothe present embodiment. The oversampling circuit shown in FIG. 5 isconfigured by four D flip-flop (D-FF)s 10-1, 10-2, 10-3, and 10-4, fourmultipliers 12-1, 12-2, 12-3, and 12-4, three adder (ADD)s 14-1, 14-2,and 14-3, and two integrating circuits 16-1 and 16-2.

The four serially connected D flip-flops 10-1 through 10-4 hold datasynchronous with a clock signal CLK, sequentially fetch the digital datainput to the first D flip-flop 10-1, and hold the value. For example,assuming that data D₁, D₂, D₃, D₄, . . . are sequentially input into thefirst D flip-flop 10-1, the third, second, and first input data D₃, D₂,and D₁ are respectively held in the second, third, and fourth Dflip-flops 10-2, 10-3, and 10-4 at the timing of holding the fourthinput data D₄ in the first D flip-flop 10-1.

Each of the four multipliers 12-1 through 12-4 has two types ofmultiplicators, and performs different multiplying processes between thefirst half and the second half of each period of the clock signal CLK.For example, the multiplier 12-1 performs the multiplying process usinga multiplicator of −1 in the first half of each period of the clocksignal CLK, and performs the multiplying process using a multiplicatorof +3 in the second half. The multiplier 12-2 performs the multiplyingprocess using a multiplicator of +5 in the first half of each period ofthe clock signal CLK, and performs the multiplying process using amultiplicator of −7 in the second half. The multiplier 12-3 performs themultiplying process using a multiplicator of −7 in the first half ofeach period of the clock signal CLK, and performs the multiplyingprocess using a multiplicator of +5 in the second half. The multiplier12-4 performs the multiplying process using a multiplicator of +3 in thefirst half of each period of the clock signal CLK, and performs themultiplying process using a multiplicator of −1 in the second half.

Each value of the step function shown in FIG. 4 can be obtained bydifferentiating twice each piecewise polynomial in the above mentionedexpressions (1) as follows.

−1;−2≦t<−3/2

+3;−3/2≦t<−1

+5;−1≦t<−1/2

−7;−1/2≦t<0

−7;0≦t<1/2

+5;1/2≦t<1

+3;1≦t<3/2

−1;3/2≦t≦2

Regarding the portion where the sampling position t ranges from −2 to−1, the values of the step function are −1 in the first half, and +3 inthe second half. These values correspond to the multiplicators of themultiplier 12-1. Similarly, regarding the portion where the samplingposition t ranges from −1 to 0, the values of the step function are +5in the first half, and −7 in the second half. These values correspond tothe multiplicators of the multiplier 12-2. Regarding the portion wherethe sampling position t ranges from 0 to +1, the values of the stepfunction are −7 in the first half, and +5 in the second half. Thesevalues correspond to the multiplicators of the multiplier 12-3.Regarding the portion where the sampling position t ranges from +1 to+2, the values of the step function are +3 in the first half, and −1 inthe second half. These values correspond to the multiplicators of themultiplier 12-4.

Each of the three adders 14-1 through 14-3 is used to add up themultiplication results of the above mentioned four multipliers 12-1through 12-4. The adder 14-1 adds up the multiplication results of thetwo multipliers 12-1 and 12-2. The adder 14-2 adds up the multiplicationresult of the multiplier 12-3 and the addition result of the adder 14-1.Furthermore, the adder 14-3 adds up the multiplication result of themultiplier 12-4 and the addition result of the adder 14-2. Using thesethree adders 14-1 through 14-3, the multiplication results of the fourmultipliers 12-1 through 12-4 are added up. Since multiplying processesare performed using different multiplicators between the first half andthe second half of each period of the clock signal CLK in each of themultipliers 12-1 through 12-4 as described above, the output value ofthe adder 14-3 obtained by adding up the multiplication results alsorefers to the digital data in the form of steps having different valuesbetween the first half and the second half of each period of the clocksignal CLK.

According to the present embodiment, four multiplication results of thefour multipliers 12-1 through 12-4 are added up by the three adders 14-1through 14-3, but the number of adders can be reduced by using an adderhaving three or more input terminals.

The two serially connected integrating circuits 16-1 and 16-2 performtwo integrating processes on the data output from adder 14-3. A linearlychanging data (like a linear function) is output from the integratingcircuit 16-1 at the first stage, and a data changing like a quadricfunction is output from the integrating circuit 16-2 at the subsequentstage.

FIG. 6 shows the detailed configuration of the integrating circuits 16-1and 16-2. The integrating circuit 16-1 at the preceding stage comprisestwo D flip-flops (D-FF) 161 a and 161 c and an adder (ADD) 161 b. Theadder 161 b has two input terminals. Data output from the adder 14-3 andtemporarily held in the D flip-flop 161 a is input into one inputterminal, and data output from the adder 161 b itself and temporarilyheld in the D flip-flop 161 c is input into the other input terminal.Each of the D flip-flops 161 a and 161 c holds the data synchronous withthe clock signal CLK2 for an integrating operation. The clock signalCLK2 corresponds to the oversampling frequency, and is set to thefrequency n times as high as the frequency of the clock signal CLK inputto the D flip-flops 10-1 through 10-4 and the multipliers 12-1 through12-4. Therefore, when the data output from the adder 14-3 is input intothe integrating circuit 16-1 with the above mentioned configuration, adigital integrating operation for accumulating the input data isperformed in synchronization with the clock signal CLK2.

The integrating circuit 16-2 at the subsequent stage has the basicallythe same configuration as the above mentioned integrating circuit 16-1at the preceding stage, and comprises two D flip-flops (D-FF) 162 a and162 c and an adder (ADD) 162 b. When data output from the integratingcircuit 16-1 at the preceding stage is input into the integratingcircuit 16-2 with the above mentioned configuration, a digitalintegrating operation for accumulating the input data is performed insynchronization with the clock signal CLK2.

Thus, when plural pieces of digital data are input into the D flip-flop10-1 at the first stage at predetermined intervals, plural pieces ofdigital data for interpolation of digital data are obtained from theintegrating circuit 16-2 at the subsequent stage.

The above mentioned D flip-flops 10-1 through 10-4 correspond to aplurality of data holding unit, the multipliers 12-1 through 12-4correspond to a plurality of multiplying unit, the adders 14-1 through14-3 correspond to adding unit, and the integrating circuits 16-1 and16-2 correspond to integrating unit.

FIGS. 7A to 7L show operation timings of the oversampling circuitaccording to the present embodiment. In synchronization with the rise ofeach period of the clock signal CLK shown in FIG. 7A, the data D₁, D₂,D₃, D₄, . . . are sequentially input into the first D flip-flop 10-1.FIGS. 7B to 7E show the contents of the data held in the D flip-flops10-1 through 10-4 respectively. In the explanation below, for example,the timing of one clock of holding the fourth input data D₄ in the firstD flip-flop 10-1 is considered.

At the timing of holding the fourth input data D₄ in the first Dflip-flop 10-1, the third input data D₃ is held in the second Dflip-flop 10-2, the second input data D₂ is held in the third Dflip-flop 10-3, and the first input data D₁ is held in the fourth Dflip-flop 10-4.

The multiplier 12-1 receives the data D₄ held in the first D flip-flop10-1, outputs in the first half of one clock period the multiplicationresult of −D₄ obtained by multiplying the input data D₄ by −1, andoutputs in the second half the multiplication result of +3D₄ obtained bymultiplying the input data D₄ by +3 (FIG. 7F). Similarly, the multiplier12-2 receives the data D₃ held in the second D flip-flop 10-2, outputsin the first half of one clock period the multiplication result of +5D₃obtained by multiplying the input data D₃ by +5, and outputs in thesecond half the multiplication result of −7D₃ obtained by multiplyingthe input data D₃ by −7 (FIG. 7G). The multiplier 12-3 receives the dataD₂ held in the third D flip-flop 10-3, outputs in the first half of oneclock period the multiplication result of −7D₂ obtained by multiplyingthe input data D₂ by −7, and outputs in the second half themultiplication result of +5D₂ obtained by multiplying the input data D₂by +5 (FIG. 7H). The multiplier 12-4 receives the data D, held in thefourth D flip-flop 10-4, outputs in the first half of one clock periodthe multiplication result of +3D, obtained by multiplying the input dataD, by +3, and outputs in the second half the multiplication result of−D₁ obtained by multiplying the input data D₁ by −1 (FIG. 7I).

The three adders 14-1 through 14-3 add up the four multiplicationresults obtained by the four multipliers 12-1 through 12-4. Therefore,in the first half of one clock period, the adder 14-3 outputs theaddition result (−D₄+5D₃−7D₂+3D₁) obtained by adding up themultiplication results obtained in the first half of one clock period bythe four multipliers 12-1 through 12-4. In the second half of one clockperiod, the adder 14-3 outputs the addition result (3D₄−7D₃+5D₂−D₁)obtained by adding up the multiplication results obtained in the secondhalf of one clock period by the four multipliers 12-1 through 12-4.

Thus, when addition results are sequentially output in the form of stepsfrom the adder 14-3 (FIG. 7J), the integrating circuit 16-1 at thepreceding stage outputs plural pieces of data whose values change in theform of the polygonal line by integrating the waveform (FIG. 7K). Theintegrating circuit 16-2 at the subsequent stage further integrates thedata whose values changes in the form of the polygonal line, and outputsplural pieces of data whose values change along a smooth curvedifferentiable only once between the digital data D₂ and D₃ (FIG. 7L).

FIGS. 8A and 8B show the details of the data output from the twointegrating circuits 16-1 and 16-2. For example, the frequency of theclock signal CLK2 for an integrating operation input into each of theintegrating circuits 16-1 and 16-2 is set to 20 times as high as thesampling frequency (frequency of the clock signal CLK) of the inputdata. As shown in FIG. 8A, the plural pieces of data output from theintegrating circuit 16-1 at the preceding stage have values changinglike a linear function. As shown in FIG. 8B, the plural pieces of dataoutput from the integrating circuit 16-2 at the subsequent stage havevalues changing like a quadric function.

In each of the integrating circuits 16-1 and 16-2 whose configurationsare shown in FIG. 6, a digital integrating process is performed bysimply accumulating input data. Therefore, since the value of the dataoutput therefrom becomes larger depending on the multiple of theoversampling, it is necessary to provide a division circuit at theoutput stage of each of the integrating circuits 16-l and 16-2 in orderto make the values of input output data coincident. For example, in theexample shown in FIG. 8, since the value of the output data is 20 timesas large as the input data, a division circuit having a divisor of 20 isprovided at the end of each of the integrating circuits 16-1 and 16-2.However, when a multiple of the oversampling is set to a value of thepower of 2 (for example, 2, 4, 8, 16, . . . ), a dividing process can beperformed on output data by bit-shifting the output data of each of theintegrating circuits 16-1 and 16-2 toward lower bits, thereby omittingthe above mentioned division circuit. For example, when the multiple ofthe oversampling is set to 16, the output data from each of theintegrating circuits 16-1 and 16-2 can be shifted by 5 bits toward lowerbits. Therefore, the wiring at the output terminal of each circuit canbe shifted by 5 bits in advance.

Thus, the oversampling circuit according to the present embodimentsequentially holds the input digital data in the four serially connectedD flip-flops 10-1 through 10-4, respectively corresponding to which fourmultipliers 12-1 through 12-4 perform different multiplying processesbetween the first half and the second half of one clock period as dataholding period. Then, the adders 14-1 through 14-3 add themultiplication results. And then, by performing a digital integratingprocess twice by the two integrating circuits 16-1 and 16-2 on the dataoutput from the adder 14-3, an oversampling process can be performed forincreasing in a pseudo manner a sampling frequency n times as high asthe frequency of each piece of the input digital data.

Thus, the oversampling circuit according to the present embodiment setshow many times the sampling frequency of the input data the oversamplingfrequency is to be set depends only on the frequency of the clock signalCLK2 input into the two integrating circuits 16-1 and 16-2. That is, themultiple of the oversampling can be set large only by configuring thetwo integrating circuits 16-1 and 16-2 using high-speed parts.Therefore, unlike the conventional method of performing the oversamplingprocess using a digital filter, the entire circuit is not large althoughthe frequency of the oversampling is set higher, thereby minimizing theincrease of the cost of parts. Furthermore, the contents of theoperations can be simplified by using the integer multiplicators of fourmultipliers 12-1 through 12-4, thereby simplifying the configuration ofthese multipliers, and reducing the cost of parts.

Furthermore, for example, when an oversampling process is performed toobtain a pseudo frequency n times as high as the sampling frequency (forexamples, 1024 times), it has been necessary in the conventional methodto have the operation speed of the parts as high as the pseudofrequency. However, according to the oversampling circuit of the presentembodiment, except the two integrating circuits, it is necessary tooperate the each multiplier and each adder at the frequency twice ashigh as the sampling frequency, thereby considerably reducing theoperation speed of each part.

Described below is an example of a detailed configuration of each partof the oversampling circuit according to the present embodiment. FIGS. 9through 12 show the configurations of the four multipliers 12-1 through12-4.

As shown in FIG. 9, the multiplier 12-1 comprises two multipliers 121 aand 121 b in which values of multiplicator are fixed, and a selector 121c. One multiplier 121 a performs a multiplying process using amultiplicator of −1, and the other multiplier 121 b performs amultiplying process using a multiplicator of +3. The selector 121 creceives the multiplication results of the two multipliers 121 a and 121b, outputs a multiplication result obtained from one multiplier 121 ausing a multiplicator of −1 when the clock signal CLK input to thecontrol terminal S indicates a high level, that is, in the first half ofone clock period, and outputs a multiplication result obtained from theother multiplier 121 b using a multiplicator of +3 when the clock signalCLK input to the control terminal S indicates a low level, that is, inthe second half of one clock period.

Similarly, the multiplier 12-2 comprises two multipliers 122 a and 122 bin which values of multiplicator are fixed, and a selector 122 c asshown in FIG. 10. One multiplier 122 a performs a multiplying processusing a multiplicator of +5, and the other multiplier 122 b performs amultiplying process using a multiplicator of −7. The selector 122 creceives the multiplication results of the two multipliers 122 a and 122b, outputs a multiplication result obtained from one multiplier 122 ausing a multiplicator of +5 when the clock signal CLK input to thecontrol terminal S indicates a high level (in the first half of oneclock period), and outputs a multiplication result obtained from theother multiplier 122 b using a multiplicator of −7 when the clock signalCLK input to the control terminal S indicates a low level (in the secondhalf of one clock period).

As shown in FIG. 11, the multiplier 12-3 comprises two multipliers 123 aand 123 b in which multiplicator values are fixed, and a selector 123 c.One multiplier 123 a performs a multiplying process using amultiplicator of −7, and the other multiplier 123 b performs amultiplying process using a multiplicator of +5. The selector 123 creceives the multiplication results of the two multipliers 123 a and 123b, outputs a multiplication result obtained from one multiplier 123 ausing a multiplicator of −7 when the clock signal CLK input to thecontrol terminal S indicates a high level (in the first half of oneclock period), and outputs a multiplication result obtained from theother multiplier 123 b using a multiplicator of +5 when the clock signalCLK input to the control terminal S indicates a low level (in the secondhalf of one clock period).

As shown in FIG. 12, the multiplier 12-4 comprises two multipliers 124 aand 124 b in which values of multiplicator are fixed, and a selector 124c. One multiplier 124 a performs a multiplying process using amultiplicator of +3, and the other multiplier 124 b performs amultiplying process using a multiplicator of −1. The selector 124 creceives the multiplication results of the two multipliers 124 a and 124b, outputs a multiplication result obtained from one multiplier 124 ausing a multiplicator of +3 when the clock signal CLK input to thecontrol terminal S indicates a high level (in the first half of oneclock period), and outputs a multiplication result obtained from theother multiplier 124 b using a multiplicator of −1 when the clock signalCLK input to the control terminal S indicates a low level (in the secondhalf of one clock period).

Thus, each multiplier performs a multiplying process using differentmultiplicators between the first half and the second half of one clockperiod.

The above mentioned four multipliers 12-1 through 12-4 use fourmultiplicators of −1, +3, +5, and −7. When 1 is subtracted from eachvalue of multiplicator, they are −2, +2, +4, and −8, that is, the valuesof the power of 2. As a result, the multiplying processes using thesevalues as multiplicators can be realized by a simple bit shift.Regarding these specific values as multiplicators of each multiplieraccording to the present embodiment, the configuration of eachmultiplier can be simplified.

FIGS. 13 through 16 show the configurations of the four simplifiedmultipliers 12-1 through 12-4.

The multiplier 12-1 comprises a tri-state buffer 121 d having aninverting output terminal, a tri-state buffer 121 e having anon-inverting output terminal, and an adder (ADD) 121 f having two inputterminals and carry terminal C as shown in FIG. 13.

When the clock signal CLK input to the control terminal indicates a highlevel (in the first half of one clock period), the tri-state buffer 121d shifts the input data to a higher bit by one bit, and inverts andoutputs each bit of the shifted data, thereby performing a multiplyingprocess by a multiplicator of −2. Actually, by obtaining a complement byadding 1 after inverting each bit, a multiplying process can beperformed using a multiplicator of −2. The process of adding 1 isperformed by the adder 121 f at the subsequent stage.

Furthermore, when the clock signal inverted and input to the controlterminal indicates a low level (in the second half of one clock period),the tri-state buffer 121 e shifts the input data to a higher bit by onebit, and outputs the data, thereby performing a multiplying process by amultiplicator of 2.

The adder 121 f adds the input data (the data output from the Dflip-flop 10-1) before the multiplication to the multiplication resultoutput from any of the two tri-state buffers 121 d and 121 e, andfurther adds 1 corresponding to the carry when the clock signal CLKinput to the carry terminal C indicates a high level (in the first halfof one clock period). As described above, the addition of 1corresponding to the carry is performed to obtain a complement using thetri-state buffer 121 d.

Since the operation of only the tri-state buffer 121 d is valid in thefirst half of one clock period in the multiplier 12-1 with the abovementioned configuration, the adder 121 f outputs a sum (−2D+D=−D)obtained by adding the input data D to the multiplication result (−2D)obtained by multiplying the input data D by −2. In the second half ofone clock period, since the operation of only the other tri-state buffer121 e is valid, the adder 121 f outputs a sum (+2D+D=+3D) obtained byadding the input data D to the multiplication result (+2D) obtained bymultiplying the input data D by +2.

Thus, by performing multiplying processes using multiplicators of −1 and+3 by combining the multiplying process of the exponentiation of 2 by abit shift with the adding process, the multiplier 12-1 can be configuredonly by tri-state buffers and an adder, thereby simplifying theconfiguration. Especially, since the output of the two tri-state buffersis selectively used, the output terminals can be wired OR-connected,thereby furthermore simplifying the configuration.

In addition, the multiplier 12-2 comprises a tri-state buffer 122 dhaving a non-inverting output terminal, a tri-state buffer 122 e havingan inverting output terminal, and an adder (ADD) 122 f having two inputterminals and a carry terminal C as shown in FIG. 14.

When the clock signal input to the control terminal indicates a highlevel (in the first half of one clock period), the tri-state buffer 122d shifts the input data to a higher bit by two bits, and outputs theshifted data, thereby performing a multiplying process by amultiplicator of +4.

When the clock signal CLK inverted and input to the control terminalindicates a low level (in the second half of one clock period), thetri-state buffer 122 e shifts and outputs the input data to a higher bitby three bits, and outputs the data after inverting each bit of theshifted data, thereby performing a multiplying process by amultiplicator of −8. Actually, by obtaining a complement by adding 1after inverting each bit, a multiplying process can be performed using amultiplicator of −8. The process of adding 1 is performed by the adder122 f at the subsequent stage.

The adder 122 f adds the input data before the multiplication to themultiplication result output from any of the two tri-state buffers 122 dand 122 e, and further adds 1 corresponding to the carry when the clocksignal CLK inverted and input to the carry terminal C indicates a lowlevel (in the second half of one clock period). As described above, theaddition of 1 corresponding to the carry is performed to obtain acomplement using the tri-state buffer 122 e.

Since the operation of only the tri-state buffer 122 d is valid in thefirst half of one clock period in the multiplier 12-2 with the abovementioned configuration, the adder 122 f outputs a sum (+4D+D=+5D)obtained by adding the input data D to the multiplication result (+4D)obtained by multiplying the input data D by +4. In the second half ofone clock period, since the operation of only the other tri-state buffer122 e is valid, the adder 122 f outputs a sum (−8D+D=−7D) obtained byadding the input data D to the multiplication result (−8D) obtained bymultiplying the input data D by −8.

Thus, by performing multiplying processes using multiplicators of +5 and−7 by combining the multiplying process of the power of 2 by a bit shiftwith the adding process, the multiplier 12-2 can be configured only bytri-state buffers and an adder, thereby simplifying the configuration.

In addition, the multiplier 12-3 comprises a tri-state buffer 123 dhaving an inverting output terminal, a tri-state buffer 123 e having anon-inverting output terminal, and an adder (ADD) 123 f having two inputterminals and a carry terminal C as shown in FIG. 15.

When the clock signal CLK inverted and input to the control terminalindicates a high level (in the first half of one clock period), thetri-state buffer 123 d shifts and outputs the input data to a higher bitby three bits, and outputs the data after inverting each bit of theshifted data, thereby performing a multiplying process by amultiplicator of −8. Actually, by obtaining a complement by adding 1after inverting each bit, a multiplying process can be performed using amultiplicator of −8. The process of adding 1 is performed by the adder123 f at the subsequent stage.

When the clock signal CLK inverted and input to the control terminalindicates a low-level (in the second half of one clock period), thetri-state buffer 123 e shifts the input data to a higher bit by twobits, and outputs the shifted data, thereby performing a multiplyingprocess by a multiplicator of +4.

The adder 123 f adds the input data before the multiplication to themultiplication result output from any of the two tri-state buffers 123 dand 123 e, and further adds 1 corresponding to the carry when the clocksignal CLK input to the carry terminal C indicates a high level (in thefirst half of one clock period). As described above, the addition of 1corresponding to the carry is performed to obtain a complement using thetri-state buffer 123 e.

Since the operation of only the tri-state buffer 123 d is valid in thefirst half of one clock period in the multiplier 12-3 with the abovementioned configuration, the adder 123 f outputs a sum (−8D+D=−7D)obtained by adding the input data D to the multiplication result (−8D)obtained by multiplying the input data D by −8. In the second half ofone clock period, since the operation of only the other tri-state buffer123 e is valid, the adder 123 f outputs a sum (+4D+D=+5D) obtained byadding the input data D to the multiplication result (+4D) obtained bymultiplying the input data D by +4.

Thus, by performing multiplying processes using multiplicators of −7 and+5 by combining the multiplying process of the power of 2 by a bit shiftwith the adding process, the multiplier 12-3 can be configured only bytri-state buffers and an adder, thereby simplifying the configuration.

In addition, the multiplier 12-4-comprises a tri-state buffer 124 dhaving a non-inverting output terminal, a tri-state buffer 124 e havingan inverting output terminal, and an adder (ADD) 124 f having two inputterminals and a carry terminal C as shown in FIG. 16.

When the clock signal input to the control terminal indicates a highlevel (in the first half of one clock period), the tri-state buffer 124d shifts the input data to a higher bit by one bit, and outputs theshifted data, thereby performing a multiplying process by amultiplicator of 2.

When the clock signal CLK inverted and input to the control terminalindicates a low level (in the second half of one clock period), thetri-state buffer 124 e shifts the input data to a higher bit by one bit,and outputs the data after inverting each bit of the shifted data,thereby performing a multiplying process by a multiplicator of −2.Actually, by obtaining a complement by adding 1 after inverting eachbit, a multiplying process can be performed using a multiplicator of −2.The process of adding 1 is performed by the adder 124 f at thesubsequent stage.

The adder 124 f adds the input data before the multiplication to themultiplication result output from any of the two tri-state buffers 124 dand 124 e, and further adds 1 corresponding to the carry when the clocksignal CLK inverted and input to the carry terminal C indicates a lowlevel (in the second half of one clock period). As described above, theaddition of 1 corresponding to the carry is performed to obtain acomplement using the tri-state buffer 124 e.

Since the operation of only the tri-state buffer 124 d is valid in thefirst half of one clock period in the multiplier 12-4 with the abovementioned configuration, the adder 124 f outputs a sum (+2D+D=+3D)obtained by adding the input data D to the multiplication result (+2D)obtained by multiplying the input data D by +2. In the second half ofone clock period, since the operation of only the other tri-state buffer124 e is valid, the adder 124 f outputs a sum (−2D+D=−D) obtained byadding the input data D to the multiplication result (−2D) obtained bymultiplying the input data D by −2.

Thus, by performing multiplying processes using multiplicators of +3 and−1 by combining the multiplying process of the power of 2 by a bit shiftwith the adding process, the multiplier 12-4 can be configured only bytri-state buffers and an adder, thereby simplifying the configuration.

A D/A converter can be configured with smaller number of parts by addinga low pass filter, etc. at the subsequent stage of the above mentionedoversampling circuit. FIG. 17 shows the configuration of the D/Aconverter. The D/A converter has the configuration obtained by adding aD/A converter 18 and a low pass filter (LPF) 20 at the subsequent stageof the oversampling circuit shown in FIG. 5.

The D/A converter 18 generates an analog voltage corresponding to thestepwise digital data output by the integrating circuit 16-2 at thesubsequent stage. The D/A converter 18 generates a constant analogvoltage proportional to the value of the input digital data, and thevoltage value at the output terminal of the D/A converter 18 alsochanges stepwise. The low pass filter 20 smoothes the output voltage ofthe DIA converter 18, and outputs a smoothly changing analog signal.

Since the D/A converter shown in FIG. 17 uses the oversampling circuitshown in FIG. 5, the configuration can be simplified and the cost ofparts can be reduced. Although an output waveform is obtained with lessdistortion and the oversampling frequency set high, the configuration isnot complicated. As a result, it can be realized to reduce the cost.

The present invention is not limited to the above mentioned embodiment,and various types of embodiments can be set within the scope of the gistof the present invention. For example, according to the above mentionedembodiment, a sampling function is defined as a function of localsupport differentiable only once in the whole range, but the times ofdifferentiation can be set to a value equal to or larger than 2. In thiscase, the number of integrating circuits is to match the number of timesof differentiation.

The sampling function of this embodiment converges to zero at t=±2, asshown in FIG. 1, but may converge to zero at t=±3 or beyond. Forexample, in a case of the sampling function converging to zero at t=±3,six D flip-flops and six multipliers may be contained in theoversampling circuit shown in FIG. 5, to interpolate for the six digitaldata.

Furthermore, it is not limited to the interpolating process using asampling function of local support, but using a sampling functiondifferentiable finite times having a predetermined value in the rangefrom −∞ to +∞, an interpolation process may be performed only for pluraldigital data corresponding to finite sample position. For example,assuming that the above mentioned sampling function is defined by aquadric piecewise polynomial, a predetermined step function waveform canbe obtained by differentiating twice each piecewise polynomial, therebyoperating a multiplier using each multiplicator corresponding to thestep function waveform.

INDUSTRIAL APPLICABILITY

As described above, according to the present invention, output datahaving values smoothly changing can be obtained by adding upmultiplication results for plural pieces of sequentially input digitaldata, and digitally integrating the addition result. Therefore, when anoversampling frequency is high, it is necessary only to speed up thedigital integration, thereby avoiding the conventional complicatedconfiguration, that is, simplifying the configuration, and reducing thecost of parts.

What is claimed is:
 1. An oversampling circuit, characterized by comprising: a plurality of data holding unit for holding each of plural pieces of digital data input at predetermined intervals; a plurality of multiplying unit for receiving said digital data held by each of said plurality of data holding unit, and performing a multiplying process using different multiplicators between a first half and a second half of a data holding period; an adding unit for performing a process of adding up multiplication results of said plurality of multiplying unit; and an integrating unit for performing a digital integrating process plural times on output data from said adding unit.
 2. The oversampling circuit according to claim 1, characterized in that each of the multiplicators used in the multiplying processes by said plurality of multiplying unit corresponds to each of the values of step functions obtained by differentiating plural times piecewise polynomials for a predetermined sampling function configured by the piecewise polynomials.
 3. The oversampling circuit according to claim 2, wherein said step function comprises a positive region and a negative region set to have an equal area.
 4. The oversampling circuit according to claim 3, wherein said sampling function is differentiable only once over the whole range and has values of local support.
 5. The oversampling circuit according to claim 2, characterized in that said step function consists of eight piecewise sections in equal width with a weight of −1, +3, +5, −7, −7, +5, +3, and −1 in a predetermined range corresponding to said five digital data arranged at an equal interval, and that every two of the eight weight coefficients are set as the multiplicators in each of said plurality of multiplying unit.
 6. The oversampling circuit according to claim 5, characterized in that a multiplying process performed in each of said plurality of multiplying unit is realized by adding said digital data to an operation result of an exponentiation of 2 by a bit shift.
 7. The oversampling circuit according to claim 1, characterized in that times of said digital integration is two, and data whose value changes like a quadric function is output from said integrating unit.
 8. The oversampling circuit according to claim 1, characterized in that said digital integration performed by said integrating unit is an operating process of accumulating input data, and n times of an oversampling process is performed by repeatedly performing the operating process n times in one period of inputting the digital data to said data holding unit.
 9. A digital-to-analog converter, comprising at a stage subsequent to said oversampling circuit according to claim 1: voltage generation unit for generating an analog voltage corresponding to a value of data output by said integrating unit; and smoothing unit for smoothing the analog voltage generated by said voltage generation unit. 